MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 219

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

4.4.1
In the case of decompression off mode, the DECRAM can serve as a two-clock access general-purpose
RAM for U-bus instruction fetches or four-clock access for read/write data operations. The base address
of the DECRAM is 0x2F 8000. See
defined by programming the R, D, and S bits of the BBCMCR register:
Freescale Semiconductor
•
•
•
ICDU
VT1 Address
Read/write or read only
Instruction/data or data only
Supervisor/user or supervisor only
General-Purpose Memory Operation
U-bus Data
Vocabulary Table (VT1)
Array
Figure 4-4. DECRAM Interfaces Block Diagram
MPC561/MPC563 Reference Manual, Rev. 1.2
(1 Kbyte)
Figure
VT1 Data
ICDU Control Logic
4-6. The proper access rights to the DECRAM array may be
VT2 Address
DECRAM
Slave BIU
Vocabulary Table (VT2)
Array
U-bus Address
(1 Kbyte)
Burst Buffer Controller 2 Module
VT2 Data
4-13