MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1190
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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TPU3 ROM Functions
D.13 Period/Pulse-Width Accumulator (PPWA)
The period/pulse-width accumulator (PPWA) algorithm accumulates a 16-bit or 24-bit sum of either the
period or the pulse width of an input signal over a programmable number of periods or pulses (from one
to 255). After an accumulation period, the algorithm can generate a link to a sequential block of up to eight
channels. The user specifies a starting channel of the block and number of channels within the block.
Generation of links depends on the mode of operation.
Any channel can be used to measure an accumulated number of periods of an input signal. A maximum of
24 bits can be used for the accumulation parameter. From one to 255 period measurements can be made
and summed with the previous measurement(s) before the TPU3 interrupts the RCPU, allowing
instantaneous or average frequency measurement, and the latest complete accumulation (over the
programmed number of periods).
The pulse width (high-time portion) of an input signal can be measured (up to 24 bits) and added to a
previous measurement over a programmable number of periods (one to 255). This provides an
instantaneous or average pulse-width measurement capability, allowing the latest complete accumulation
(over the specified number of periods) to always be available in a parameter.
By using the output compare function in conjunction with PPWA, an output signal can be generated that
is proportional to a specified input signal. The ratio of the input and output frequency is programmable.
One or more output signals with different frequencies, yet proportional and synchronized to a single input
signal, can be generated on separate channels. See Freescale TPU Progamming Note Period/Pulse-Width
Accumulator TPU Function (PPWA), (TPUPN11/D).
Figure D-24
D-38
shows the host interface areas and parameter RAM for the PPWA function.
NAME
Figure D-23. FQD Parameters — Secondary Channel
MPC561/MPC563 Reference Manual, Rev. 1.2
CONTROL BITS
OPTIONS
See
PRAM Address Offset Map.
Table 19-24
ADDRESSES
Freescale Semiconductor
for the
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