MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 619

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC561MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Chapter 15
Queued Serial Multi-Channel Module
The MPC561/MPC563 contains one queued serial multi-channel module (QSMCM). The QSMCM
provides three serial communication interfaces: the queued serial peripheral interface (QSPI) and two
serial communications interfaces (SCI/UART). These submodules communicate with the CPU via a
common slave bus interface unit (SBIU).
The QSPI is a full-duplex, synchronous serial interface for communicating with peripherals and other
MCUs. It is enhanced from the original SPI in the QSMCM (queued serial module) to include a total of
160 bytes of queue RAM to accommodate more receive, transmit, and control information.
The duplicate, independent SCIs are full-duplex universal asynchronous receiver transmitter (UART)
serial interface. The original QSM SCI is enhanced by the addition of an SCI, a common external baud
clock source, receive and transmit buffers on one SCI. The SCIs are fully compatible with the SCI systems
found on other Freescale MCUs. The dual, independent SCI, DSCI, submodule is used to communicate
with external devices and other MCUs via an asynchronous serial bus. The DSCI has all of the capabilities
of previous SCI systems as well as several significant new features. The following paragraphs describe the
features, pins, programming model (memory map), registers, and the transmit and receive operations of
the DSCI.
The SBIU provides an interface between the QSMCM module and the intermodule bus (IMB3).
15.1
Block Diagram
Figure 15-1
shows the major components of the QSMCM.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
15-1

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