MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 71
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Table
Number
SHORT_REG[SH_TCAN] Bit Settings ............................................................................... 18-20
SHORT_REG[SH_TPU] Bit Settings .................................................................................. 18-21
SHORT_CH_REG Bit Descriptions..................................................................................... 18-23
Examples of the SHORT_CH Bits ....................................................................................... 18-23
SCALE_TCLK Frequencies ................................................................................................. 18-24
SCALE_TCLK_REG Bit Descriptions ................................................................................ 18-24
TPU Memory Map.................................................................................................................. 19-1
Enhanced TCR1 Prescaler Divide Values .............................................................................. 19-6
TCR1 Prescaler Values ........................................................................................................... 19-6
TCR2 Counter Clock Source .................................................................................................. 19-7
TCR2 Prescaler Control.......................................................................................................... 19-8
TPU3 Register Map ................................................................................................................ 19-8
TPUMCR Bit Description .................................................................................................... 19-11
DSCR Bit Descriptions ......................................................................................................... 19-12
DSSR Bit Descriptions ......................................................................................................... 19-14
TICR Bit Description............................................................................................................ 19-15
CIER Bit Descriptions .......................................................................................................... 19-15
CFSRn Bit Descriptions........................................................................................................ 19-16
HSQRn Bit Descriptions....................................................................................................... 19-17
HSSRn Bit Descriptions ....................................................................................................... 19-18
CPRn Bit Description ........................................................................................................... 19-18
Channel Priorities ................................................................................................................. 19-18
CISR Bit Descriptions .......................................................................................................... 19-19
TPUMCR2 Bit Descriptions ................................................................................................. 19-19
Entry Table Bank Location................................................................................................... 19-20
System Clock Frequency/Minimum Guaranteed Detected Pulse......................................... 19-20
TPUMCR3 Bit Descriptions ................................................................................................. 19-21
SIUTST Bit Descriptions...................................................................................................... 19-22
Registers Used for Factory Test Only .................................................................................. 19-22
Parameter RAM Address Offset Map .................................................................................. 19-23
DPTRAM Register Map ......................................................................................................... 20-3
DPTMCR Bit Settings ............................................................................................................ 20-4
RAMBAR Bit Settings ........................................................................................................... 20-5
UC3F External Interface Signals ............................................................................................ 21-4
UC3F Register Programming Model ...................................................................................... 21-5
UC3FMCR Bit Descriptions................................................................................................... 21-6
UC3FMCRE Bit Descriptions ................................................................................................ 21-9
UC3FCTL Bit Descriptions .................................................................................................. 21-11
RCW Bit Descriptions .......................................................................................................... 21-17
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
Title
Number
Page
lxxi
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