MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1407

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC561MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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I-bus
ICDU
ICTRL A-16
ID
IDE 16-6
Identifier (ID) 16-1
IDLE 15-49
Idle
IFLAG 16-36
Ignore first match 23-52
IIFM 23-52
ILBS 12-4
ILIE 15-48
illegal and reserved instructions, 3-40
ILSCI 15-9
ILT 15-47
IMASK 16-35
IMB 13-47
IMB clock 12-2
IMMR 6-28
implementation dependent software emulation
implementation specific data TLB error interrupt, 3-58
implementation specific debug interrupt, 3-59
implementation specific instruction TLB error
IMUL–IDIV 3-5
Information processing time (IPT) 16-10
Initial sample time 13-35
Input
Instruction
Instruction fetch
Freescale Semiconductor
watchpoint programming 23-51
features A-1
Extended (IDE) field 16-6
HIGH field 16-6
LOW field 16-6
bit field for standard format 16-6
CAN status (IDLE) 16-34
frame 15-52
-line
sample time (IST) 13-31
pipeline 3-38
sequencer 3-3
set summary 3-28
timing 3-37
show cycle control 23-1
detect type (ILT) 15-47
detected (IDLE) 15-49
detection process 15-58
interrupt enable (ILIE) 15-48
type (ILT) bit 15-58
interrupt, 3-56
interrupt, 3-57
,
,
,
15-58
,
,
,
15-58
14-48
15-10
A-18
15-58
,
16-34
,
,
A-18
14-36
,
,
13-49
15-58
,
,
,
15-58
14-32
A-17
MPC561/MPC563 Reference Manual, Rev. 1.2
instruction storage interrupt, 3-48
instruction support 23-14
instructions
instructions, partially executed, 3-60
Integer exception register 3-18
Integer unit 3-5
interchannel communication 19-4
Intermission 16-17
internal bus arbiter 9-35
Interrupt
interrupt
interrupt controller
interrupt level byte select 12-4
Interrupt Level of SCI (ILSCI) 15-9
Interrupts
interrupts
interrupts, 3-45
Inter-transfer delay 15-15
Interval timer single-scan mode 13-44
invalid and preferred instructions, 3-40
Invalid channel number 13-31
IPT 16-10
IRAMSTBY 8-23
IRQ 19-5
ISCTL 23-1
IST 13-31
IU 3-5
IW 23-51
IWPn 23-30
IWPnand VFLSn 23-30
J
JTAG
K
KAPWR 8-22
keep alive power 8-24
keep-alive power 22-5
KR/RETRY, 9-5
cache control, 3-43
storage control, 3-45
register (QADCINT) 13-7
external 3-48
enhanced 6-8
TOUCAN 16-20
TPU 19-5
MIOS 17-63
UIMB 12-3
instruction register 25-30
pin diagram 25-1
reset 7-3
registers 8-26
,
,
A-17
13-49
,
,
14-32
22-5
,
13-12
,
,
14-11
15-10
,
14-45
Index-7

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