MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 812

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC561MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Peripheral Pin Multiplexing (PPM) Module
SCALE_TCLK_REG. The transmit signals, PPM_TX, will stay high as long as PPM_TSYNC is high
(equal to “1” in
Complete transmit and receive cycles are based on the PPM_TSYNC clock. A cycle begins on the rising
edge of PPM_TSYNC, which goes high for one PPM_TCLK cycle. The transmit signals, PPM_TX[0:1],
will stay high as long as PPM_TSYNC is high (equal to “1” in
the falling edge of PPM_TSYNC. In receive mode, valid data starts to shift into RX_SHIFTER on the
falling edge of PPM_TSYNC. PPM_TSYNC stays low until the contents of TX_DATA have been shifted
out and/or 16 bits have been shifted into RX_SHIFTER. One data bit is transferred every PPM_TCLK
cycle.
18-6
PPM_TSYNC
PPM_TCLK1
PPM_TCLK2
PPM_TCLK2
PPM_RX
PPM_TX
SYSCLK
(see
PPM_TCLK1 — TCLK in TDM Mode
PPM_TCLK2 — TCLK in SPI Mode
PPM_CLK2 — TCLK in SPI Mode, with inverted SPI clock polarity enabled
f
TCLK
Section 18.4.12, “ Scale Transmit Clock Register (SCALE_TCLK_REG)
= (f
Figure
Shading of PPM_RX signifies value is unknown
SYSCLK
18-5).
/2*N) where N is the value in SCALE_TCLK_REG
Figure 18-5. PPM Clocks and Serial Data Signals
MPC561/MPC563 Reference Manual, Rev. 1.2
“1”
CHANNEL0
CHANNEL0
Figure
CHANNEL1
CHANNEL1
18-6). Data bits start to transmit on
CHANNEL2
CHANNEL2
Freescale Semiconductor

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