MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1109

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
1
2
Single Segment Full
Compression
Twin Segments Full
Compression
Twin Segments Full
Compression With
Swapped Vocabularies
(Vocabulary In RAM #2
For MSB Segment)
Left Segment
Compression, Right
Segment Bypassed,
Vocabulary In RAM #1
Left Segment
Compression, Right
Segment Bypassed,
Vocabulary In RAM #2
Left Segment Bypassed,
Right Segment
Compression,
Vocabulary In RAM #1
Left Segment Bypassed,
Right Segment
Compression,
Vocabulary In RAM #2
X1, X2 - pointers to vocabularies
BP - the bypassed data
Configuration
Configu
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
CLASS
ration
Code
2a
2b
3a
3b
4b
4a
1
MPC561/MPC563 Reference Manual, Rev. 1.2
Table A-4. Instruction Layout Encoding
to RAM
1 and 2
Points
TP1
#
1
1
2
1
2
to RAM
Bypass
Points
TP2
—
#
2
RAM # Vocab. RAM # Vocab.
TP1BA Points
—
—
1
1
1
1
to
V1
V1
V2
V1
V2
—
—
TP2BA Points
—
—
2
2
2
2
MPC562/MPC564 Compression Features
to
V2
V2
V1
V1
V2
—
—
AS DS
—
—
0
1
0
1
—
0
1
0
1
Compressed
Instruction
X1 BP
X1 BP
X2 BP
X2 BP
Layout
X1 X2
X2 X1
X1
1
2
2
2
2
A-21