MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1373
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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G.22 MPIOSM Timing Characteristics
Note: All delays are in system clock periods.
Freescale Semiconductor
1
2
MPIOSM input pin period
MPIOSM pin low time
MPIOSM pin high time
Input pin to MPIOSM_DR delay
Output pulse width
MDASM interrupt flag
The minimum input pin period, pin low and pin high times depend on the rate at which the MPIOSM_DR
register is polled.
The minimum output pulse width depends on how quickly the CPU updates the value inside the MIOPSM_DR
register.
Counter bus[15:0]
MDASMAR[15:0]
MPIOSM input pins
Figure G-62. MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram
Figure G-61. Counter Bus to MDASM Interrupt Flag Setting Timing Diagram
MPIOSM_DR
Characteristic
f
SYS
2
f
SYS
5AFC
5AFE
Table G-27. MPIOSM Timing Characteristics
MPC561/MPC563 Reference Manual, Rev. 1.2
FFA5
5AFD
FFA5
t
Output mode
PDR
Input Mode
Symbol
t
t
t
PULW
PPER
t
t
PLO
PDR
PHI
005A
005A
t
5AFE
CBFLG
Min
—
—
—
—
0
1
1
1
2
66-MHz Electrical Characteristics
Max
—
—
—
—
1
G-67
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