MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 724
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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CAN 2.0B Controller Module
16.7.7
16-30
10:12
13:15
SRESET
Bits
8:15
Bits
0:7
0:7
8:9
Field
Addr
Control Register 2 (CANCTRL2)
CANCTRL2
PRESDIV
PRESDIV
MSB
PSEG1
PSEG2
Name
0
Name
RJW
1
0x30 7088 (CANCTRL2_A); 0x30 7488 (CANCTRL2_B); 0x30 7888 (CANCTRL2_C)
Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency
and the serial clock (S-clock). The S-clock is determined by the following calculation:
The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same
frequency as the system clock. The valid programmed values are 0 through 255.
See
See
Resynchronization jump width. The RJW field defines the maximum number of time quanta
a bit time may be changed during resynchronization. The valid programmed values are zero
through three.
The resynchronization jump width is calculated as follows:
PSEG1[2:0] — Phase buffer segment 1. The PSEG1 field defines the length of phase buffer
segment one in the bit time. The valid programmed values are zero through seven.
The length of phase buffer segment 1 is calculated as follows:
PSEG2 — Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer
segment two in the bit time. The valid programmed values are zero through seven.
The length of phase buffer segment two is calculated as follows:
2
Resynchronizaton Jump Width = (RJW + 1) Time Quanta
Phase Buffer Segment 1 = (PSEG1 + 1) Time Quanta
Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta
Table
Table
Figure 16-14. Control Register 2 (CANCTRL2)
PRESDIV
3
Table 16-18. CANCTRL2 Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 16-17. PRESDIV Bit Descriptions
16-18.
16-17.
4
5
0000_0000_0000_0000
6
S-clock
7
=
----------------------------------- -
PRESDIV
Description
Description
8
RJW
f SYS
9
+
1
10
PSEG1
11
12
Freescale Semiconductor
13
PSEG2
Eqn. 16-1
14
LSB
15
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