MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 680

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Queued Serial Multi-Channel Module
15.8.3
The block diagram of the enhancements to the SCI transmitter is shown in
15-62
12:15
Bits
8:11
5
6
7
QSCI1 Transmitter Block Diagram
QRPNT
QPEND
QBHE
Name
QBHF
QTHE
Receiver queue bottom-half full. QBHF is set when the receive queue locations SCRQ[8:15] are
completely filled with new data received via the serial shifter. QBHF is cleared when register
QSCI1SR is read with QBHF set, followed by a write of QBHF to zero.
0 The queue locations SCRQ[8:15] are partially filled with newly received data or is empty
1 The queue locations SCRQ[8:15] are completely full of newly received data
Transmitter queue top-half empty. QTHE is set when all the data frames in the transmit queue
locations SCTQ[0:7] have been transferred to the transmit serial shifter. QTHE is cleared when
register QSCI1SR is read with QTHE set, followed by a write of QTHE to zero.
0 The queue locations SCTQ[0:7] still contain data to be sent to the transmit serial shifter
1 New data may now be written to the queue locations SCTQ[0:7]
Transmitter queue bottom-half empty. QBHE is set when all the data frames in the transmit queue
locations SCTQ[8:15] has been transferred to the transmit serial shifter. QBHE is cleared when
register QSCI1SR is read with QBHE set, followed by a write of QBHE to zero.
0 The queue locations SCTQ[8:15] still contain data to be sent to the transmit serial shifter
1 New data may now be written to the queue locations SCTQ[8:15]
Queue receive pointer. QRPNT is a 4-bit counter used to indicate the position where the next
valid data frame will be stored within the receive queue. This field is writable in test mode only;
otherwise it is read-only.
Queue pending. QPEND is a 4-bit decrementer used to indicate the number of data frames in the
queue that are awaiting transfer to the SC1DR. This field is writable in test mode only; otherwise
it is read-only. From 1 (QPEND = 0b0000) to 16 (or done, QPEND = 1111) data frames can be
specified.
Table 15-33. QSCI1SR Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Figure
15-33.
Freescale Semiconductor