MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 703

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

the system clock and the CAN bit segments. Refer to
information on the bit timing registers.
A bit is divided into four separate non-overlapping time segments called SYNC_SEG, PROPSEG, PSEG1,
and PSEG2. These are illustrated in
the segment durations:
The sample point indicated in
bit is selected (CANCTRL1[SAMP] bit = 0). If three samples per bit are selected, the sample point
indicated in
Freescale Semiconductor
t
SYSTEM
CLOCK
S-CLOCK
TIME
QUANTUM
Transmit
point
NBT
System Clock
SS
Frequency
Figure 16-5
= t
(MHz)
56
40
25
20
16
56
40
25
20
SYNC_SEG
Table 16-8. Example System Clock, CAN Bit Rate, and S-Clock Frequencies
SYNC_SEG
Figure 16-5. Relationship between System Clock and CAN Bit Segments
SS
CAN Bit Rate
+ t
marks the position of the final sample.
(MHz)
0.500
0.500
0.500
0.500
PROPSEG
1
1
1
1
1
Figure 16-5
PROPSEG
MPC561/MPC563 Reference Manual, Rev. 1.2
Baud Rate Prescaler (PRESDIV)
+ t
Figure
Possible S-Clock
Frequency (MHz)
PSEG1
Nominal bit time (NBT)
is the position of the actual sample point if a single sample per
16-5. The period of the nominal bit time (NBT) is the sum of
1, 2, 2.5
10, 20
+ t
8, 16
56
40
25
56
40
25
PSEG2
PSEG1
Section 16.7, “Programming
Sample point
Possible Number of
Time Quanta/Bit
10, 20
2, 4, 5
8, 16
118
56
40
25
80
50
PSEG2
PRESDIV Value + 1
CAN 2.0B Controller Module
Model,” for more
20, 10, 8
2, 1
2, 1
1
1
1
1
1
1
16-9