MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 811

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

18.3.1.2
The PPM module generates and outputs two clock signals, PPM_TCLK and PPM_TSYNC. The
PPM_TCLK and PPM_TSYNC clocks are the basis for all PPM communication functions; single data bits
are transmitted and received on PPM_TCLK cycles, one PPM_TSYNC clock cycle defines a single 16-bit
word transmit/receive cycle. The PPM can be configured to transfer data in one of two clock modes, SPI
and TDM.
PPM_TCLK is a function of the system clock (SYSCLK) and is programmable using the
Freescale Semiconductor
A_TPUCH15
B_TPUCH15
A_TPUCH0
B_TPUCH0
A_TPUCH15
B_TPUCH15
A_TPUCH0
B_TPUCH0
Figure 18-5
MPWM0
GPDO15
MDA14
MPWM0
PPM Clocks
GPDO0
MDA14
Figure 18-4. Internal Multiplexer Mechanism for Received Data
Figure 18-3. Internal Multiplexer Mechanism for Transmit Data
shows examples of PPM_TCLK in SPI and TDM modes. The frequency of
MPC561/MPC563 Reference Manual, Rev. 1.2
RX_CONFIG[CH0]
RX_CONFIG[CH15]
TX_CONFIG[CH15]
TX_CONFIG[CH0]
CH15
CH15
CH15
CH15
RX_DATA
GPDI
RX_SHIFTER
TX_SHIFTER
• • •
• • •
• • •
• • •
Peripheral Pin Multiplexing (PPM) Module
RX_CONFIG[CHx]
CH0
CH0
CH0
CH0
PPM_RX[0:1]
PPM_TX[0:1]
•
18-5