MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 561

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
Bits
3:7
0
1
2
8
RESUME
Name
SSE2
CIE2
PIE2
MQ2
of queue 2. The interrupt request is initiated when the conversion is complete for the CCW in
queue 2.
0 Disable the queue completion interrupt associated with queue 2
1 Enable an interrupt after the conversion of the sample requested by the last CCW in queue
the pause state. The interrupt request is initiated when conversion is complete for a CCW that
has the pause bit set.
0 Disable the pause interrupt associated with queue 2
1 Enable an interrupt after the conversion of the sample requested by a CCW in queue 2
Queue 2 Single-Scan Enable Bit. SSE2 enables a single-scan of queue 2 to start after a
trigger event occurs. The SSE2 bit may be set to a one during the same write cycle when the
MQ2 bits are set for one of the single-scan queue operating modes. The single-scan enable
bit can be written as a one or a zero, but is always read as a zero. The SSE2 bit enables a
trigger event to initiate queue execution for any single-scan operation on queue 2. The
QADC64E clears the SSE2 bit when the single-scan is complete. Refer to
more information.
0 Trigger events are not accepted for single-scan modes
1 Accept a trigger event to start queue 2 in a single-scan mode
Queue 2 Operating Mode. The MQ2 field selects the queue operating mode for queue 2.
Refer to
0 After suspension, begin executing with the first CCW in queue 2 or the current sub-queue
1 After suspension, begin executing with the aborted CCW in queue 2
Queue 2 Completion Software Interrupt Enable. CIE2 enables an interrupt upon completion
Queue 2 Pause Software Interrupt Enable. PIE2 enables an interrupt when queue 2 enters
2
which has the pause bit set
Table 14-14
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 14-13. QACR2 Bit Descriptions
for more information.
Description
QADC64E Enhanced Mode Operation
Table 14-14
for
14-19