MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 848

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Time Processor Unit 3
19.4.9
The channel priority registers (CPR1, CPR2) assign one of three priority levels to a channel or disable the
channel. See
19-18
SRESET
SRESET
Field
Addr
Field
Addr
CH[15:0]
CH[15:0]
Name
Name
MSB
MSB
Channel Priority Registers (CPRx)
0
0
CH 15
Appendix D, “TPU3 ROM
CH 7
Encoded type of host service. The host service request field selects the type of host service request for
the time function selected on a given channel. The meaning of the host service request bits depends
on the time function specified.
A host service request field cleared to 0b00 signals the host that service is completed by the
microengine on that channel. The host can request service on a channel by writing the corresponding
host service request field to one of three non-zero states. The CPU must monitor the host service
request register until the TPU3 clears the service request to 0b00 before any parameters are changed
or a new service request is issued to the channel.
Encoded channel priority levels.
channel priority encoding.
1
1
2
2
CH 14
CH 6
Figure 19-18. CPR0 — Channel Priority Register 0
Figure 19-19. CPR1 — Channel Priority Register 1
3
3
CHx[1:0]
MPC561/MPC563 Reference Manual, Rev. 1.2
00
01
10
11
Table 19-14. HSSRn Bit Descriptions
4
Table 19-15. CPRn Bit Description
4
CH 13
CH 5
Table 19-16. Channel Priorities
0x30 401C (TPU_A), 0x30 441C (TPU_B)
0x30 401E (TPU_A), 0x30 441E (TPU_B)
Functions,” for more information.
5
5
Disabled
Service
Table 19-16
Middle
High
Low
0000_0000_0000_0000
0000_0000_0000_0000
6
6
CH 12
CH 4
Description
7
Description
7
indicates the number of time slots guaranteed for each
Guaranteed Time Slots
8
8
CH 11
1 out of 7
2 out of 7
4 out of 7
CH 3
—
9
9
10
10
CH 10
CH 2
11
11
12
12
CH 9
CH 1
Freescale Semiconductor
13
13
14
14
CH 0
CH 8
LSB
LSB
15
15