MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 917
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Table 23-2
23.1.1.2
The history buffer flushes status pins denote how many instructions are flushed from the history buffer this
clock due to an
Freescale Semiconductor
1
2
VF[0:2]
Unless next clock VF=111. See below.
The sequential instructions listed here affect the machine in a manner similar to indirect branch instructions. Refer
to
000
001
010
011
100
101
110
111
Section 23.1.3, “Sequential Instructions Marked as Indirect
shows VF[0:2] encodings for instruction queue flush information.
History Buffer Flushes Status Pins— VFLS [0:1]
None
Sequential
Branch (direct or indirect) not taken
VSYNC was asserted/negated and therefore the
next instruction will be marked with the indirect
change-of-flow attribute
Exception taken — the target will be marked with the
indirect change-of-flow attribute
Branch indirect taken, rfi, mtmsr, isync and in some
cases mtspr to CMPA-F, ICTRL, ECR, or DER — the
target will be marked with the indirect change-of-flow
attribute
Branch direct taken
Branch (direct or indirect) not taken
exception.Table 23-3
2
1
VF[0:2]
Refer to
000
001
010
011
100
101
110
111
Instruction Type
Table 23-2. VF Pins Queue Flush Encodings
Table 23-1. VF Pins Instruction Encodings
MPC561/MPC563 Reference Manual, Rev. 1.2
Table
0 instructions flushed from instruction queue
1 instruction flushed from instruction queue
2 instructions flushed from instruction queue
3 instructions flushed from instruction queue
4 instructions flushed from instruction queue
5 instructions flushed from instruction queue
Reserved
Instruction type information
shows VFLS encodings.
23-1.
Queue Flush Information
Branch.”
1
More instruction type information
More instruction type information
More instruction type information
More instruction type information
Queue flush information
Queue flush information
Queue flush information
Queue flush information
VF Next Clock Will Hold
1
1
1
1
Development Support
23-3
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