MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 654

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Queued Serial Multi-Channel Module
15.6.5.3
The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or user-specified (DSCK
= 1) delay from chip-select assertion until the leading edge of the serial clock. The DSCKL field in SPCR1
determines the length of the user-defined delay before the assertion of SCK. The following expression
determines the actual delay before SCK when DSCKL is in the range of 1–127:
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transition is one-half the
SCK period.
15.6.5.4
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted
between consecutive transfers to allow serial A/D converters to complete conversion. Writing a value to
the DTL field in SPCR1 specifies a delay period. The DT bit in each command RAM byte determines
whether the standard delay period (DT = 0) or the specified delay period (DT = 1) is used. The following
expression is used to calculate the delay:
A zero value for DTL causes a delay-after-transfer value of 8192 ÷ IMB3 clock frequency (204.8 µs with
a 40-MHz IMB3 clock).
If DT is zero in a command RAM byte, a standard delay is inserted.
15-36
Delay Before Transfer
Delay After Transfer
Table 15-21. Example SCK Frequencies with a 40-MHz IMB3 Clock (continued)
where DTL is in the range from one to 255.
A zero value for DSCKL causes a delay of 128 IMB3 clocks, which equals
3.2 µs for a 40-MHz IMB3 clock. Because of design limits, a DSCKL value
of one defaults to the same timing as a value of two.
Division Ratio
MPC561/MPC563 Reference Manual, Rev. 1.2
PCS to SCK Delay
280
510
14
28
58
Standard Delay after Transfer
Delay after Transfer
SPBR Value
NOTE
140
255
14
29
=
7
DSCKL
------------------- -
f SYS
=
32xDTL
-------------------- -
f SYS
Frequency
78.43 kHz
2.86 MHz
1.43 MHz
689 kHz
143 kHz
=
SCK
-------------
f SYS
17
Freescale Semiconductor
Eqn. 15-3