MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 247

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Figure 6-2
Freescale Semiconductor
Path of Write Operation
Path of Read Operation
SGPIO Circuitry
Internal
Bus
1
SGPIOD[16:23]
SGPIOD[24:31]
SGPIOA[16:23]
SGPIOA[24:31]
Read
Write
SGPIOD[8:15]
Configuration Register
SGPIOC[0:7]
SGPIOA[8:15]
Group Name
SGPIOD[0:7]
SGPIOC[0:7] is selected according to GPC and MLRC fields in SIUMCR. See
Clock
SGPIO
illustrates the functionality of the SGPIO.
1
GPIO
Write
Register
Pin Control
Individual
Figure 6-2. Circuit Paths of Reading and Writing to SGPIO
(SIUMCR).”
X
X
MPC561/MPC563 Reference Manual, Rev. 1.2
SDDRD[23:31]
SDDRC[0:7]
Direction
Control
GDDR0
GDDR1
GDDR2
GDDR3
GDDR4
GDDR5
Table 6-2. SGPIO Configuration
Read Path
When SC = 00
Write Path
(32-bit Port
Size Mode)
Available
When SC = 01
(16-bit Port
Size Mode)
Available
X
X
GPIO
Read
Register
Section 6.2.2.1.1, “SIU Module
When SC = 10
(Single-Chip
System Configuration and Protection
Mode with
Available
Trace)
X
X
X
X
Write
Read
When SC = 11
(Single-Chip
OE
Available
SGPIO
Mode)
Pad
X
X
X
X
X
X
X
6-7