MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 319

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Table 8-6
8.7.2
Table 8-5
8.7.3
Exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt
generated by the interrupt controller. Any enabled asynchronous interrupt clears the LPM bits but does not
change the PLPRCR[CSRC] bit.
Freescale Semiconductor
Normal-low (“gear”)
Operation Mode
summarizes the control bit settings for the different clock power modes.
describes the clock frequency and chip functionality for each power mode.
SRAM Standby
Normal-high
Power-down
Deep-sleep
Power Mode Descriptions
Exiting from Low-Power Modes
Doze-high
Doze-low
Sleep
Not active
Not active
Not active
Active
Active
Active
Active
Active
SPLL
Normal-low (“gear”)
Table 8-4. Power Mode Control Bit Settings
Power Mode
Normal-high
Power-down
Deep-sleep
MPC561/MPC563 Reference Manual, Rev. 1.2
Doze-high
Doze-low
Table 8-5. Power Mode Descriptions
Sleep
Full frequency ÷
Full frequency ÷
Full frequency ÷
Full frequency ÷
Not active
Not active
Not active
Not active
2
2
Clocks
2
2
DFNL+1
DFNL+1
DFNH
DFNH
LPM[0:1]
00
00
01
01
10
11
11
Full functions not in use
Enabled: RTC, PIT, TB
(RCPU, BBC, FPU)
Enabled: RTC, PIT,
Disabled: extended
CSRC
Functionality
TB and DEC,
SRAM data
are shut off
1
X
X
X
0
0
1
and DEC
controller
retention
core
TEXPS
X
X
X
X
X
1
0
VDD, QVDDL, NVDDL,
VDD, QVDDL, NVDDL,
Power Pins that Need
KAPWR, IRAMSTBY
KAPWR, IRAMSTBY
KAPWR, VDDSYN,
KAPWR, VDDSYN,
KAPWR, VDDSYN,
to be Powered-Up
IRAMSTBY
IRAMSTBY
IRAMSTBY
IRAMSTBY
Clocks and Power Control
All On
All On
8-17