MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1105

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
12:13
14:15
16:17
18:19
Bits
9:11
0:2
3:5
6:8
20
21
22
23
24
25
26
27
Mnemonic
DIWP0EN
DIWP1EN
DIWP2EN
DIWP3EN
SIWP0EN
SIWP1EN
SIWP2EN
SIWP3EN
IWP0
IWP2
IWP3
CTC
CTD
CTB
CTA
W1
Compare type of comparator A
Compare type of comparator B
Compare type of comparator C
Compare type of comparator D
I-bus 1st watchpoint
programming
I-bus 2nd watchpoint
programming
I-bus 3rd watchpoint
programming
I-bus 4th watchpoint
programming
Software trap enable selection of
the 1st I-bus watchpoint
Software trap enable selection of
the 2nd I-bus watchpoint
Software trap enable selection of
the 3rd I-bus watchpoint
Software trap enable selection of
the 4th I-bus watchpoint
Development port trap enable
selection of the 1st I-bus
watchpoint (read only bit)
Development port trap enable
selection of the 2nd I-bus
watchpoint (read only bit)
Development port trap enable
selection of the 3rd I-bus
watchpoint (read only bit)
Development port trap enable
selection of the 4th I-bus
watchpoint (read only bit)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Table A-1. ICTRL Bit Descriptions
0xx = not active (reset value)
100 = equal
101 = less than
110 = greater than
111 = not equal
0x = not active (reset value)
10 = match from comparator A
11 = match from comparators (A&B)
0x = not active (reset value)
10 = match from comparator B
11 = match from comparators (A | B)
0x = not active (reset value)
10 = match from comparator C
11 = match from comparators (C&D)
0x = not active (reset value)
10 = match from comparator D
11 = match from comparators (C | D)
0x = not active (reset value)
10 = match from comparator D
11 = match from comparators (C | D)
0 = trap disabled (reset
value)
1 = trap enabled
0 = trap disabled (reset
value)
1 = trap enabled
Non-compressed mode
MPC562/MPC564 Compression Features
Function
1xx = not active
000 = equal (reset value)
001 = less than
010 = greater than
011 = not equal
0 = trap disabled (reset
value)
1 = trap enabled
0 = trap disabled (reset
value)
1 = trap enabled
Compressed Mode
1
A-17