MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1395
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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READI development control register
READI device ID register
READI DID
READI DTA 1 and DTA 2 (READI data trace attributes 1
and 2 registers)
READI RWA (READI read/write access register)
READI UBA (READI user base accress register)
READI UDI (READI upload/download information regis-
ter)
Region attribute register (0 - 3)
Register diagrams
Freescale Semiconductor
24-15
floating-point exception cause register (FPECR)
floating-point registers (FPRs)
floating-point status and control register (FPSCR)
general special-purpose registers (SPRG0-SPRG3)
general-purpose registers (GPRs)
implementation-specific
integer exception register (XER)
link register (LR)
machine state register (MSR)
machine status save/restore register 0 (SRR0)
machine status save/restore register 1 (SRR1)
OEA register set
processor version register (PVR)
UISA register set
VEA register set - time base
CALRLAM_OTR (CALRAM ownership trace regis-
CANCTRL0 (control register 0)
CANCTRL1 (control register 1)
CANCTRL2 (control register 2)
CFSR0 (TPU3 channel function select register 0)
CFSR1 (TPU3 channel function select register 1)
CFSR2 (TPU3 channel function select register 2)
CFSR3 (TPU3 channel function select register 3)
CIER (TPU3 channel interrupt enable register)
CISR (TPU3 channel interrupt status register)
CMPG-CMPH (comparator G-H value registers)
COUNTA (breakpoint counter A value and control
CPR0 (TPU3 channel priority register 0)
CPR1 (TPU3 channel priority register 1)
CRAM_RBAx (CALRAM region base address regis-
24-9
3-13
3-24
3-25
ter)
19-16
19-16
19-16
19-16
23-47
register)
ter)
24-17
22-18
22-16
3-20
3-12
23-45
3-19
24-9
special-purpose
4-22
3-20
3-20
3-12
16-27
16-28
16-30
24-10
3-18
3-25
3-12
MPC561/MPC563 Reference Manual, Rev. 1.2
,
24-11
19-18
19-18
24-12
registers
24-13
3-23
3-23
19-19
19-15
3-26
CRAMMCR (CALRAM module configuration regis-
CRAMOVL (CALRAM overlay configuration regis-
DDRQA (QADC64E port A data direction registers)
DDRQS (PORTQS data direction register)
DER (debug enable register)
DSCR (TPU3 development support control register)
DSSR (TPU3 development support status register)
ECR (exception cause register)
EIBADR (external interrupt relocation table base ad-
HSQR0 (TPU3 host sequence register 0)
HSQR1 (TPU3 host sequence register 1)
HSSR0 (TPU3 host service request register 0)
HSSR1 (TPU3 host service request register 1)
IMASK (interrupt mask register)
L2U_GRA (L2U global region attribute register)
L2U_MCR (L2U module configuration register)
L2U_RAx (L2U region X attribute register)
L2U_RBAx (L2U region x base address register)
LCTRL2 (L-bus support control register 2)
MIOS14SR0 (interrupt status register)
MIOS14SR1 (interrupt status register)
MIOS1LVL0 (MIOS1 interrupt level register 0)
MIOS1LVL1 (MIOS1 interrupt level 1 register)
MISCNT (MISC counter)
MISRH (multiple input signature register high)
MISRL (multiple input signature register low)
PORTQS (port QS data register)
PQSPAR (PORTQS pin assignment register)
PRESDIV (prescaler divide register)
QACR1 (QADC64E control register 1)
QADCMCR (module configuration register)
QSCI1CR (QSCI1 control register)
QSCI1SR (QSCI1 status register)
QSMCMMCR (QSMCM module configuration regis-
QSPI_IL (QSPI interrupt level register)
READI DTA 1 and DTA 2 (READI data trace at-
Region attribute register (0 - 3)
SCCxR0 (QSMCM SCI control register 0)
ter)
ter)
13-14
19-12
19-14
dress register)
11-16
11-14
11-14
17-69
17-70
14-16
ter)
tributes 1 and 2 registers)
22-13
22-17
15-8
,
14-14
4-25
20-6
23-43
23-42
4-22
,
21-5
15-12
16-35
15-61
24-17
15-60
16-29
17-67
,
17-66
21-9
15-10
19-17
19-17
RegIndex-3
15-14
15-46
23-48
11-15
13-8
15-13
,
13-16
19-17
19-17
20-6
17-68
20-5
,
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