MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 230
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Burst Buffer Controller 2 Module
4-24
1
20:21
22:24
26:27
29:31
This field is available only on the MPC562/MPC564.
Bits
4:19
25
28
0
1
2
3
BTBINH
CMPR
Name
ENR0
ENR1
ENR2
ENR3
The MI_GRA register should be programmed to enable fetch access (PP and
G bits) before RCPU MSR[IR] is set.
PP
—
—
—
G
1
Enable IMPU Region 0
0 Region 0 is off.
1 Region 0 is on.
Enable IMPU Region 1
0 Region 1 is off.
1 Region 1 is on.
Enable IMPU Region 2
0 Region 2 is off.
1 Region 2 is on.
Enable IMPU Region 3
0 Region 3 is off.
1 Region 3 is on.
Reserved
Protection Bits
00 Supervisor – No Access, User – No Access.
01 Supervisor – Fetch, User – No Access.
1x Supervisor – Fetch, User – Fetch.
Reserved
Guard attribute for region
0 Fetch is not prohibited from region. Region is not guarded.
1 Fetch is prohibited from guarded region. An exception will occur under such attempt.
Compressed Region.
x0 The region is not restricted
01 Region is considered a non-compressed code region Access to the region is allowed only in
11 Region is considered a compressed code region. Access to the region is allowed only in
BTB Inhibit region
0 BTB operation is not prohibited for current memory region
1 BTB operation is prohibited for current memory region.
Reserved
“Decompression Off” mode
“Decompression On” mode
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 4-8. MI_GRA Field Descriptions
NOTE
Description
Freescale Semiconductor
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