MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1408

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

L
L2U 11-1
L2U module configuration register (L2U_MCR) 11-13
L2U_GRA 11-16
L2U_MCR 11-13
L2U_RAx 11-15
L2U_RBAx 11-14
LBRK 23-43
LBUF 16-29
L-bus support
L-bus to U-bus interface unit 11-1
LCTRL1 23-47
LCTRL2 23-48
LE bit 3-22
Least significant bit (LSB) 13-36
Length of delay after transfer (DTL) 15-19
Link register 3-19
Little endian mode 3-22
LJSRR 13-33
LJURR 13-33
Load/store unit 3-4
Lock
Loop
LOOPQ 15-21
LOOPS 15-47
low power stop 6-23
Low power stop (LPSTOP)
Lowest buffer transmitted first (LBUF) 16-29
Low-power
LR 3-5
LSB 13-36
LSU 3-4
LW0EN 23-49
LW0IA 23-49
LW0IADC 23-49
LW0LA 23-49
LW0LADC 23-49
LW0LD 23-49
LW0LDDC 23-49
LW1EN 23-49
LW1IA 23-49
LW1IADC 23-49
LW1LA 23-50
Index-8
modes of operation 11-3
control register 1 23-47
control register 2 23-48
/release/busy mechanism 16-16
mode
QSM 15-6
stop mode enable (STOP)
(LOOPS) 15-47
TPU 19-11
,
3-19
,
3-6
,
14-38
,
,
14-35
14-35
,
3-6
,
14-38
MPC561/MPC563 Reference Manual, Rev. 1.2
LW1LADC 23-50
LW1LD 23-50
LW1LDDC 23-50
M
M 15-47
MA 13-14
Machine
Machine check
machine check
mapping
Mask
Master
master
MBISM 17-13
MC 24-11
MCE 23-42
MCEE 23-43
MCIE bit 3-47
MCPSM 17-16
MCPSMSCR 17-18
MCPWM D-22
MDASM submodule 17-70
MDASMAR 17-41
MDASMBR 17-42
MDASMSCR 17-44
MDASMSCRD 17-43
ME bit 3-21
memory controller
memory map 1-11
Message
check enable 3-21
state register 3-20
status save/restore register 0 3-23
status save/restore register 1 3-23
enable 3-47
exception
dual 10-26
EEPROM 10-24
examples for normal/extended messages 16-8
registers (RX) 16-7
/slave mode select (MSTR) 15-18
external
registers 10-31
TPU 19-1
buffer
enable 3-47
arbitration phase 9-32
address map 16-24
code for RX/TX buffers 16-5
deactivation 16-14
structure 16-4
,
15-52
,
3-47
,
D-30
Freescale Semiconductor