MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 207
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 4
Burst Buffer Controller 2 Module
The burst buffer controller module (BBC) consists of four main functional parts: the bus interface unit
(BIU), the instruction memory protection unit (IMPU), branch target buffer (BTB) and the instruction code
decompressor unit (ICDU). See
Figure
4-1. Information about decompression features of the BBC is found
in
Appendix A, “MPC562/MPC564 Compression
Features.”
The BBC master BIU interfaces between the RCPU instruction port and the internal U-bus and can support
burstable and non-burstable U-bus accesses.
The IMPU allows the instruction memory to be divided into four regions with different protection
attributes. The IMPU compares the attributes of the RCPU memory access request with the attributes of
the appropriate region. If the access is allowed, the proper signals are sent to the BIU. If access to the
memory region is disallowed because the region is protected, an interrupt is sent to the RCPU and the
master BIU cancels U-bus access.
The IMPU is able to relocate the RCPU exception vectors. The IMPU always maps the exception vectors
into the internal memory space of the MPC561/MPC563. This feature is important for a
multi-MPC561/MPC563 system, where, although the internal memories of some controllers are not
shifted to the lower 4 Mbytes, they can still have their own internal exception vector tables with the same
exception addresses issued by their RCPU cores.
The IMPU also supports an MPC561/MPC563-enhanced interrupt controller by extending an exception
vector’s relocation mechanism to translate the RCPU external interrupt exception vector separately and
splitting it into 48 different vectors, corresponding to the code generated by the interrupt controller. See
also
Section 6.1.4.4, “Enhanced Interrupt Controller
Operation.”
The branch target buffer (BTB) improves the performance of the MPC561/MPC563 by holding and
supplying previously accessed or decompressed instructions to the RCPU core. The BTB can be enabled
in either decompression on or off mode.
The ICDU provides decompressed instructions to RCPU in the decompression ON mode and contains a 2
Kbyte RAM (DECRAM) to hold decompression vocabularies. The DECRAM can serve as a general
purpose RAM memory on the U-bus if code compression is not used.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-1
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