MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 503

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC561MZP56

Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC561MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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The queue operating mode selected for queue 1 determines what type of trigger event causes the execution
of each of the sub-queues within queue 1. Similarly, the queue operating mode for queue 2 determines the
type of trigger event required to execute each of the sub-queues within queue 2.
For example, when the external trigger rising edge continuous-scan mode is selected for queue 1, and there
are six sub-queues within queue 1, a separate rising edge is required on the external trigger signal after
every pause to begin the execution of each sub-queue (refer to
“Scan
The choice of single-scan or continuous-scan applies to the full queue, and is not applied to each
sub-queue. Once a sub-queue is initiated, each CCW is executed sequentially until the last CCW in the
sub-queue is executed and the pause state is entered. Execution can only continue with the next CCW,
which is the beginning of the next sub-queue. A sub-queue cannot be executed a second time before the
overall queue execution has been completed. Refer to
more information.
Trigger events which occur during the execution of a sub-queue are ignored, except that the trigger overrun
flag is set. When a continuous-scan mode is selected, a trigger event occurring after the completion of the
Freescale Semiconductor
BQ2
00
63
Modes,” for information on different scan modes.
P
P
P
Conversion Command Word
0
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
BEGIN Queue 1
END OF Queue 1
END OF Queue 2
BEGIN Queue 2
(CCW) Table
PAUSE
PAUSE
PAUSE
PAUSE
PAUSE
PAUSE
Figure 13-23. QADC64E Queue Operation with Pause
MPC561/MPC563 Reference Manual, Rev. 1.2
Conversion
Hold, And
Channel
Select,
Sample,
A/D
Section 13.3.7, “Control Register 2
Figure
13-23). Refer to
Result Word Table
QADC64E Legacy Mode Operation
Section 13.5.4,
QADC64E CQP
(QACR2),” for
00
63
13-39

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