MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 430

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Memory Controller
10.9.2
10.9.3
10-32
,
,
1
2
HRESET(BR[1:3])
HRESET(BR[1:3])
12:15
HRESET
Bits
8:11
The reset value is determined by the value on the internal data bus during reset (reset-configuration word).
See
0:7
HRESET(BR0)
HRESET(BR0)
Field
Addr
Table 10-9
Memory Controller Status Registers (MSTAT)
Memory Controller Base Registers (BR0–BR3)
WPER0 –
WPER3
MSB
Name
0
Field
—
—
Addr
for reset value.
1
MSB
BA
16
0
Reserved
Write protection error for bank x. This bit is asserted when a write-protect error occurs for the
associated memory bank. A bus monitor (responding to TEA assertion) will, if enabled, prompt
the read of this register if TA is not asserted during a write cycle. WPERx is cleared by writing
one to the bit or by performing a system reset. Writing a zero has no effect on WPER.
Reserved
Figure 10-23. Memory Controller Base Registers 0–3 (BR0–BR3)
Unchanged
2
Figure 10-22. Memory Controller Status Register (MSTAT)
17
1
3
0x2F C100 (BR0); 0x2F C108 (BR1); 0x2F C110 (BR2); 0x2F C118 (BR3)
—
AT
18
2
MPC561/MPC563 Reference Manual, Rev. 1.2
4
19
Table 10-7. MSTAT Bit Descriptions
3
5
ID[4:5]
20
4
PS
6
21
5
SST WP
7
22
6
0000_0000_0000_0000
00
WPER0 WPER1 WPER2 WPER3
23
7
0x2F C178
8
Unchanged
Unchanged
Unchanged
Undefined
Description
—
24
8
BA
9
BL WEBS TBDIP LBDIP SETA
25
9
10
26
10
0
11
27
11
Undefined
12
28
12
Freescale Semiconductor
13
29
13
—
14
14
30
BI
1
LSB
LSB
ID3
15
X
15
31
V
2