MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1263
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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F.12
Note: (V
Freescale Semiconductor
DD
1
2
49a
55a
43
44
45
46
47
48
49
50
51
52
53
54
55
Weak pull-ups and pull-downs used for Reset timing will comply with the 130 µA mode select current
outlined in <XrefBlue>Table F.5 on page F-7 The system requires two clocks of hold time on
RSTCONF/TEXP after negation of HRESET. The simplest way to insure meeting this requirement in
systems that require the use of the TEXP function, is to connect RSTCONF/TEXP to SRESET.
HRESET, SRESET and PORESET have a glitch detector to ensure that spikes less than 20 ns are rejected.
The internal HRESET, SRESET and PORESET will assert only if these signals are
asserted for more than 100 ns
RESET Timing
= 2.6 V ± 0.1 V, V
CLKOUT to HRESET high
impedance
CLKOUT to SRESET high
impedance
RSTCONF pulse width
Configuration Data to HRESET
rising edge Setup Time
Configuration Data to RSTCONF
rising edge set up time
Configuration Data hold time after
RSTCONF negation
Configuration Data hold time after
HRESET negation
RSTCONF hold time after HRESET
negation
HRESET and RSTCONF asserted to
Data out drive
RSTCONF negated to Data out high
impedance
CLKOUT of last rising edge before
chip tristates HRESET to Data out
high impedance
DSDI, DSCK set up
DSDI, DSCK hold time
SRESET negated to CLKOUT
rising edge for DSDI and DSCK
sample
HRESET, SRESET, PORESET
pulse width
1
Characteristic
2
DDH
= 5.0 V ± 0.25 V, T
MPC561/MPC563 Reference Manual, Rev. 1.2
Table F-14. RESET Timing
A
= T
15 * TC + TCC
15 * TC + TCC
L
Expression
to T
17 * TC
3 * TC
8 * TC
H
)
Min
425
382
382
200
100
50
25
25
25
75
0
0
0
40 MHz
Max
20
20
Min
302
272
272
142
100
35
25
25
25
55
0
0
0
56 MHz
Max
Electrical Characteristics
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
F-47
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