MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 670

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Queued Serial Multi-Channel Module
Frame
Data frame
Idle frame
Break frame
15.7.7.2
All data frames must have a start bit and at least one stop bit. Receiving and transmitting devices must use
the same data frame format. The SCI provides hardware support for both 10-bit and 11-bit frames. The M
bit in SCCxR1 specifies the number of bits per frame.
The most common data frame format for NRZ (non-return to zero) serial interfaces is one start bit, eight
data bits (Lsb first), and one stop bit (ten bits total). The most common 11-bit data frame contains one start
bit, eight data bits, a parity or control bit, and one stop bit. Ten-bit and 11-bit frames are shown in
Table
15.7.7.3
The SCI baud rate is programmed by writing a 13-bit value to the SCxBR field in SCI control register zero
(SCCxR0). The baud rate is derived from the MCU IMB3 clock by a modulus counter. Writing a value of
zero to SCxBR[12:0] disables the baud rate generator. The baud rate is calculated as follows:
15-52
1
The MSB data bit can also serve as a second STOP bit. By setting this bit permanently to one, communication with
other SCIs requiring two STOP bits could be accommodated.
15-29.
Start
Start
1
1
1
1
1
1
Serial Formats
Baud Clock
A start bit, a specified number of data or information bits, and at least one stop bit.
A frame that consists of consecutive ones. An idle frame has no start bit.
A frame that consists of consecutive zeros. A break frame has no stop bits.
A complete unit of serial information. The SCI can use 10-bit or 11-bit frames.
Data
Data
7
7
8
8
8
9
11-Bit Frames
10-bit Frames
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-29. Serial Frame Formats
Parity/Control
Parity/Control
SCI Baud Rate
—
—
—
—
1
1
or
=
----------------------------- -
32xSCxBR
f SYS
STOP
STOP
2
2
1
1
1
1
1
M
M
0
0
0
1
1
1
SCCxR1 Bits
SCCxR1 Bits
Freescale Semiconductor
PE
PE
0
1
0
1
1
0
Eqn. 15-4