HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 87

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_CTRL
Common control register
0
1
2
3
4
5
7..6
R_RAM_ADDR0
Address pointer, register 0
1st address byte for internal / external SRAM access.
7..0
Bits
Bits
0
0
0
0
0
0
0
0x00
Value
Value
Reset
Reset
(reserved)
V_RAM_ADDR0
Name
(reserved)
V_FIFO_LPRIO
V_SLOW_RD
V_EXT_RAM
(reserved)
V_CLK_OFF
Name
Universal external bus interface
(write only)
(write only)
Data Sheet
Description
Must be ’0’.
FIFO access priority for host accesses
’0’ = normal priority
’1’ = low priority
One additional wait cycle for PCI read accesses
’0’ = normal operation
’1’ = additional wait (must be set for 66 MHz PCI
operation)
Use external RAM
The internal SRAM is switched off when external
SRAM is used.
’0’ = internal SRAM is used in lower 32 kByte
address space
’1’ = external SRAM is used
Must be ’0’.
CLK oscillator
’0’ = normal operation
’1’ = CLK oscillator is switched off
This bit is reset at every write access to the
HFC-E1.
Must be ’00’.
Description
Address bits 7 . . . 0
Cologne
Chip
87 of 272
0x01
0x08