HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 79

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

32 bit processors can either write data with byte, word or double word access. Only 8 bit are
used for address decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A double word write is shown in Figure 2.18. FIFO write access have 8 bit, 16 bit or 32 bit
width alternatively. The 32 bit processor must support byte access because all other register
write accesses must have a width of 8 bit.
/BE3 . . . /BE0 control the bus lines AD31 . . . AD0 during data phase (see Table 2.22).
Data is written with
a data setup time
Address and /BE require a setup time
of these lines is
register address write is not required.
An 8 bit write access (low byte) is performed in the same way as it is done with 8 bit proces-
sors. Thus see Figure 2.14 for the timing specification.
March 2003 (rev. A)
HFC-E1
/WR+/CS
AD[31:8]
/BE[3:0]
A[7:0]
ALE
/RD
Figure 2.18: Write access from 32 bit processors in mode 4 (Intel, multiplexed)
t
address
ALE
Ø
byte enable
Ø
t
AS
address
À
Ï Ë
. If two consecutive write accesses are on the same address, multiple
of /WR
t
AH
and a data hold time
t
ALEH
Universal external bus interface
·
/CS in mode 4 (Intel, multiplexed). The HFC-E1 requires
Ø
double word write access
Data Sheet
Ë
t
t
DWRS
WR
permanently high
which starts with the
data
data
Ø
Ï À
.
t
DWRH
t
IDLE
of ALE. The hold time
double word write access
t
t
WR
DWRS
data
data
Cologne
Chip
t
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DWRH