HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 114

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
flow mode (Channel Select Mode enabled / disabled) and the operation mode of the HDLC
controller (transparent or HDLC mode). The subchannel controller allows to process less
than 8 bits of the transferred FIFO data bytes.
A general overview of the subchannel processor in transmit direction is given in Figure 3.11.
It shows an example with three FIFOs connected to one HFC-channel. Details of subchannel
processing are described in the following sections, categorized into the different modes of
the data flow and the HDLC controller.
The essence of the subchannel processor is a bit extraction (transmit) respectively insertion
(receive) unit for every FIFO and a byte mask for every HFC-channel. The subchannel
parameters V_BIT_CNT and V_START_BIT of the register A_SUBCH_CFG define the
bits of the HFC-channel byte that are claimed by the FIFO. On the other side, the channel
mask defines the bit values of those HFC-channel data bits, that are not occupied by FIFO
data.
Registers
The FIFO bit extraction / insertion requires two register settings. V_BIT_CNT defines the
number of bits to be extracted / inserted. The start bit can be selected with V_START_BIT
in the range of 0 . . . 7. Both values are located in the register A_SUBCH_CFG[FIFO].
The channel mask can be stored in the register A_CH_MSK[FIFO]. This mask is only used
for transmit data. The processed FIFO bits are stored in this register, so it must be re-
initialized after changing the settings in A_SUBCH_CFG[FIFO]. Each HFC-channel has
its own mask byte. To write this byte for HFC-channel [
written into the R_FIFO register first. After this index selection the desired mask byte
can be written with A_CH_MSK =
114 of 272
Figure 3.11: General structure of the subchannel processor shown with an example of three connected FIFOs
byte m2
byte m2
byte m3
byte m3
FIFO m
FIFO m
byte m1
byte m1
byte n2
byte n2
byte n3
byte n3
byte o2
byte o2
byte o3
byte o3
FIFO n
FIFO n
byte n1
byte n1
FIFO o
FIFO o
byte o1
byte o1
...
...
...
FIFO data output
FIFO data output
FIFO data output
FIFO data output
FIFO data output
FIFO data output
7
7
7
0
0
0
Ñ
.
Data Sheet
Data flow
7
FIFO
FIFO
data
data
o
o
channel mask
channel mask
FIFO
FIFO
data
data
Ò
m
m
,TX] the HFC-channel must be
FIFO
FIFO
data
data
m
m
FIFO
FIFO
data
data
m
m
FIFO
FIFO
data
data
n
n
FIFO
FIFO
data
data
March 2003 (rev. A)
n
n
0
channel byte
channel byte
Cologne
Chip
Ñ