HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 179

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

6.1 PCM interface function
The PCM interface has up to 32, 64 or 128 time slots for receive and transmit data depending
on the PCM clock frequency and the selected mode. The functional block diagram is shown
in Figure 6.1.
The HFC-E1 has two PCM data pins STIO1 and STIO2 which can both be input or output.
PCM output data is transmitted to two output buffers. These can be enabled independently
from each other. PCM input data can either come from one of the two PCM data pins or
from the PCM output channel. This way PCM data can be looped internally.
6.2 PCM initialization
After hard or soft reset the PCM interface starts an initialization sequence to set all A_SL_CFG
registers of the PCM time slots to the reset value 0. This can be done only if valid C4IO and
F0IO signals exist. The initialization process stops after 2 F0IO periods. To check if the ini-
tialization sequence is finished after a reset, the register R_F0_CNTL value must be equal
or greater than 2.
6.3 External CODECs
External CODECs can be connected to the HFC-E1 PCM interface. There are two ways of
programming the PCM–CODEC–interconnection. First, a set of eight CODEC enable lines
March 2003 (rev. A)
HFC-E1
CHANNEL
CHANNEL
Enable Memory
Enable Memory
Transmit Slot
Receive Slot
Read for
Write for
[1]
[7]
Figure 6.1: PCM interface function block diagram
CHANNEL
CHANNEL
Data Channel
Data Channel
Transmit Slot
Receive Slot
Select for
Select for
PCM interface
[2]
[6]
SLOT
SLOT
Data Sheet
PCM data out
PCM
data out
Receive Slot
Input Buffer
Select for
[5]
A
B
C
Buffer Enable for
Buffer Enable for
STIO0 Output
STIO1 Output
Transmit Slot
Transmit Slot
[3]
[4]
Cologne
Chip
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STIO1
STIO2