HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 141

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

(See Table 4.3 for reset value.)
(See Table 4.3 for reset value.)
(See Table 4.3 for reset value.)
March 2003 (rev. A)
HFC-E1
A_Z12 [FIFO]
FIFO input counters
Before reading this array register the FIFO must be selected by the register R_FIFO.
31..0
A_F1 [FIFO]
FIFO input HDLC frame counter
This address can also be accessed with word width to read the
together (see register A_F12).
Before reading this array register the FIFO must be selected by the register R_FIFO.
7..0
A_F2 [FIFO]
FIFO output HDLC frame counter
Before reading this array register the FIFO must be selected by the register R_FIFO.
7..0
Bits
Bits
Bits
Value
Value
Value
Reset
Reset
Reset
V_Z12
V_F1
V_F2
Name
Name
Name
½
FIFO handling and HDLC controller
and
¾
½
(read only)
(read only)
(read only)
Data Sheet
¾
Description
Bits [15..0] are counter value of ½ and bits
[31..16] are counter value of ¾
Description
Counter value
Up to 31 HDLC frames (resp. 15 with 32k RAM)
can be stored in each FIFO.
Description
Counter value
Up to 31 HDLC frames (resp. 15 with 32k RAM)
can be stored in each FIFO.
½
- and
¾
-counters
Cologne
Chip
141 of 272
0x0C
0x0D
0x04