HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 127

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
A_CHANNEL [FIFO]
HFC-channel assignment for the selected FIFO
This register is only used in Channel Select Mode and FIFO Sequence Mode.
Before writing this array register the FIFO must be selected by register R_FIFO.
0
5..1
7..6
A_FIFO_SEQ [FIFO]
FIFO sequence list
This register is only used in FIFO Sequence Mode.
Before writing this array register the FIFO must be selected by register R_FIFO.
0
5..1
6
7
Bits
Bits
0
0
0
0
0
0
0
Value
Value
Reset
Reset
V_CH_NUM0
V_NEXT_FIFO_NUM
Name
V_CH_DIR0
(reserved)
Name
V_NEXT_FIFO_DIR
V_SEQ_END
(reserved)
FIFO handling and HDLC controller
(write only)
(write only)
Data Sheet
Description
HFC-channel data direction
’0’ = HFC-channel for transmit data
’1’ = HFC-channel for receive data
HFC-channel number
(0 . . . 31)
Must be ’00’.
Description
FIFO data direction
This bit defines the data direction of the next FIFO
in FIFO sequence.
’0’ = transmit FIFO data
’1’ = receive FIFO data
FIFO number
This bitmap defines the FIFO number of the next
FIFO in FIFO sequence.
End of FIFO list
’0’ = FIFO list goes on
’1’ = FIFO list is terminated after this FIFO
(V_NEXT_FIFO_DIR and
V_NEXT_FIFO_NUM are ignored)
Must be ’0’.
Cologne
Chip
127 of 272
0xFC
0xFD