HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 236

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
12.5 Register description
12.5.1 Write only register
236 of 272
R_IRQMSK_MISC
Miscellaneous interrupt status mask register
’0’ means that the interrupt is not used for generating an interrupt on the inter-
rupt pin 197.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Reset
Value
Name
V_STA_IRQMSK
V_TI_IRQMSK
V_PROC_IRQMSK
V_DTMF_IRQMSK
V_IRQ1S_MSK
V_SA6_IRQMSK
V_RX_EOMF_MSK
V_TX_EOMF_MSK
Clock, reset, interrupt, timer and watchdog
(write only)
Data Sheet
Description
State of state machine changed interrupt mask
bit
Timer elapsed interrupt mask bit
Processing / nonprocessing transition interrupt
mask bit
(every 125 s)
DTMF detection interrupt mask bit
1 second interrupt mask bit
SA6 pattern changed or external interrupt mask
bit
Receive end of multiframe mask bit
Transmit end of multiframe mask bit
March 2003 (rev. A)
Cologne
Chip
0x11