HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 196

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Cologne
HFC-E1
PWM
Chip
The HFC-E1 has two PWM output lines PWM0 and PWM1 with programmable output
characteristic.
The output lines can be configured as open drain, open source and push / pull by setting
V_PWM0_MD respectively V_PWM1_MD in the register R_PWM_MD.
7.1 Standard PWM usage
The duty cycle of the output signals can be set in the registers R_PWM0 and R_PWM1.
The register value 0 generates an output signal which is permanently low. The register value
defines the number of clock periods where the output signal is high during the cycle time
½
Ì ¾
ÅÀÞ ¾
¼ Ò× ½¼ ¾ ×
¡
¡
¾
for the normal system clock 24.576 MHz.
The ouput signal of the PWM unit can be used for analog settings by using an external RC
filter which generates a voltage that can be adapted by changing the PWM register value.
7.2 Alternative PWM usage
The PWM output lines can be programmed to generate a 16 kHz signal. This signal can
be used as analog metering pulse for POTS interfaces. Each PWM output line can be
switched to 16 kHz signal by setting V_PWM0_16KHZ or V_PWM1_16KHZ in the regis-
ter R_RAM_MISC. In this case the output characteristic is also determined by the R_PWM_MD
register settings.
196 of 272
Data Sheet
March 2003 (rev. A)