HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 166

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
166 of 272
R_SYNC_OUT
E1 synchronization source selection for PCM master
0
4..1
5
6
7
Bits
0
0
0
0
Reset
Value
Name
V_SYNC_E1_RX
(reserved)
V_IPATS0
V_IPATS1
V_IPATS2
(write only)
E1 interface
Data Sheet
Description
PCM master synchronization
’0’ = PCM master synchronizes on the E1 TX end
of frame (EOF) signal
’1’ = PCM master synchronizes on the E1 RX end
of frame (EOF) signal
Must be ’00000’.
RAI pulse configuration for IPATS test
’0’ = normal opeartion
’1’ = delete short RAI low pulses, increase RAI to a
minimum of more than 1 ms
Note: This bit is only used for passing IPATS test
equipment.
CRC configuration for IPTAS test
’0’ = normal operation
’1’ = delete CRC reporting over E-bits up to 8 ms
after MFA synchronization
Note: This bit is only used for passing IPATS test
equipment.
JATT configuration for IPATS test
’0’ = normal operation
’1’ = stop jitter attenuator (JATT) adaptation when
in F3 or G3 state
Note: This bit is only used for passing IPATS test
equipment.
March 2003 (rev. A)
Cologne
Chip
0x31