HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 157

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_RX0
E1 receiver configuration register 0
1..0
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
Value
Reset
V_RX_CODE
Name
V_RX_FBAUD
V_RX_CMI
V_RX_INV_CMI
V_RX_INV_CLK
V_RX_INV_DATA
V_AIS_ITU
(write only)
E1 interface
Data Sheet
Description
Receive code
’00’ = NRZ (pin R_A is data input and pin R_B is
clock input in NRZ mode)
’01’ = HDB3 code
’10’ = AMI code
’11’ = reserved
Full / half bauded
’0’ = receive pulse is half bit long
’1’ = receive pulse is full bit long
Code mark inversion (CMI)
’0’ = CMI off
’1’ = CMI on
In CMI mode pin R_B is not used.
Inverted CMI code
This bit is only valid if CMI is on.
’0’ = CMI code
’1’ = inverted CMI code
Polarity of clock
This bit is only valid if data clock input is used
(NRZ mode).
’0’ = clock is not inverted
’1’ = clock is inverted
Polarity of input data
’0’ = non-inverted data
’1’ = inverted data
AIS alarm specification
’0’ = according to ETS 300233
’1’ = according to ITU-T G.775
Cologne
Chip
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