HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 104

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
3.4.2 Channel Select Mode
The Channel Select Mode (CSM) allows an arbitrary assignment between a FIFO and the
connected HFC-channel as shown in Figure 3.6 (left side). Beyond this, it is possible to
connect several FIFOs to one HFC-channel (Fig. 3.6, right side). This works in transmit and
receive direction and can be used to allocate only one 8 kByte/s E1 time slot or PCM time
slot with multiple data streams with lower data rate of the assigned FIFOs. In this case the
subchannel processor is involved.
The Channel Select Mode is selected with V_CSM_MD
register R_FIFO_MD.
104 of 272
➌ PCM-to-E1
A direct PCM-to-E1 coupling is shown in the last connection set. FIFO[12,TX] and
FIFO[12,RX] contain the data flow settings, so they must be configured and enabled to
switch on the data transmission.
G
In Simple Mode for every used FIFO[
This is valid in reverse case, too.
Rule
A_CON_HDLC[13,RX] : V_DATA_FLOW
R_SLOT
A_SL_CFG[23,RX]
A_CON_HDLC[12,TX] : V_DATA_FLOW
R_SLOT
A_SL_CFG[22,TX]
A_CON_HDLC[12,RX] : V_DATA_FLOW
R_SLOT
A_SL_CFG[22,RX]
R_FIFO
R_FIFO
R_FIFO
: V_FIFO_DIR
: V_FIFO_NUM
: V_SL_DIR
: V_SL_NUM
: V_CH_DIR1
: V_CH_NUM1
: V_FIFO_DIR
: V_FIFO_NUM
: V_SL_DIR
: V_SL_NUM
: V_CH_DIR1
: V_CH_NUM1
: V_FIFO_DIR
: V_FIFO_NUM
: V_SL_DIR
: V_SL_NUM
: V_CH_DIR1
: V_CH_NUM1
Data Sheet
Data flow
Ò
] the HFC-channel[
0
’110’
0
1
1
13
’001’
1
23
1
12
22
12
1
12
’110’
1
22
0
13
12
½
and V_FSM_MD
(transmit FIFO)
(E1
(receive HFC-channel)
(receive FIFO)
(FIFO
(receive slot)
(receive HFC-channel)
(FIFO #12)
(transmit slot)
(slot #22)
(HFC-channel #12)
(receive FIFO)
(E1
(receive slot)
(transmit HFC-channel)
(FIFO #13)
(slot #23)
(HFC-channel #13)
(FIFO #12)
(slot #22)
(HFC-channel #12)
Ò
] is also used.
PCM)
PCM)
PCM)
March 2003 (rev. A)
Cologne
Chip
¼
in the