HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 149

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

In R_RX_FR1 and R_TX_FR2 double frame or multiframe format is selectable. Double
frame format uses a simple synchronization algorithm (see Figure ??) and Multiframe format
uses the CRC4 procedure (see Figure ??).
There are several bits to configure different behavior of the time slot 0 synchronization data.
Time slot 0 data can be generated automatically according to the selected mode or can be
generated by FIFO data or from a special area in the RAM of the HFC-E1. If the RAM buffer
is used the area is organized as an alternating buffer. So one half can be read or written by the
host processor when the other half sends or receives via the E1 interface. V_RX_SL0_RAM
in register R_RX_FR1 and V_TX_SL0_RAM in register R_TX_FR2 switch between the
RAM area and the HFC-channel[0] as data destination / source.
The registers R_RX_FR0 and R_RX_FR1 are for the selection of different synchonisation
options and how slot 0 of the E1 interface is interpreted. R_TX_FR0, R_TX_FR1 and
R_TX_FR2 are used for the selection of different slot 0 data generation.
The HFC-E1 includes an elastic buffer in receive and transmit direction which can be 0
. . . 3 times 125 s. Bigger buffers lead to more delay between receive or transmit data in the
FIFOs or the PCM interface and real data on the E1 interface.
The registers R_RX_OFF and R_TX_OFF are used for buffer size selection and buffer
initialisation. After initialisation the buffers are FIFOs. In the register R_SLIP a bit is set
when there is a buffer underrun or overrun. This is reported only when the full 4 frame FIFO
is not enough to handle the data without a slip. Two other bits are slip detection bits which
remain set after a slip until the R_SLIP register is read.
The loss of receive signal (LOS) condition can be set in the registers R_LOS0 and R_LOS1.
A LOS condition is reported in the bit V_SIG_LOS of the register R_RX_STA0 and by
changing the state of the state machine accordingly.
The Receiving Alarm Indication Signal (AIS) is reported in the bit V_AIS of the register
R_RX_STA0. Sending of AIS can be switched on with V_AIS_OUT in register R_TX1.
Some receive status bits in the rigisters R_RX_STA1 . . . R_RX_STA3 are readable but
only for some diagnostic purpose. These bits are only valid for 125 s or those related to a
multiframe are valid for 2 ms.
There are 6 error counters of 16 bit size in the HFC-E1 interface. They can operate
in 2 modes. If V_AUTO_ERR_RES is 0 then they function as normal counters. If
V_AUTO_ERR_RES is 1 then every second the counter value is latched and the counter
starts again with 0.
March 2003 (rev. A)
HFC-E1
E1 interface
Data Sheet
Cologne
Chip
149 of 272