HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 48

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
48 of 272
Max_Lat
Register is implemented, value can be set by EEPROM
Register is implemented
Register is not implemented and returns all 0's when read
BIST
Data
Status Register
Subsystem ID
3
Device ID
Expansion ROM Base Address
PMC
Class Code
Memory Base Address
Reserved
CardBus CIS Pointer
Min_Gnt
Header
PMCSR
I/O Base Address
Figure 2.3: PCI configuration registers
Type
Universal external bus interface
BSE
Base Address 2
Base Address 3
Base Address 4
Base Address 5
2
Reserved
Byte
Subsystem Vendor ID
Next Item
Interrupt
Data Sheet
Latency
Command Register
Timer
Pin
Ptr
1
Vendor ID
PMCSR
Cache Line
Revision
Cap_Ptr
Interrupt
Cap_ID
Size
Line
ID
0
Hex Address
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
44h
March 2003 (rev. A)
Cologne
Chip