HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 220

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
The HFC-E1 has an auxiliary interface which is designed for connecting up to 8 external
devices with the universal bus interface. This bridge functionality supports 8 bit data bus
and up to 12 address lines. The auxiliary-to-host bridge is typically used to realize a PCI
bridge or a PCMCIA bridge for external devices. The auxiliary interface is implemented
parallel to the optional external SRAM interface, so it can only be used if no external SRAM
is connected to the HFC-E1.
11.1 Interface pins
The auxiliary bridge must be switched on with V_BRG_EN
Table 11.2 shows that the bridge functionality uses some HFC-E1 pins in their second func-
tion. As the first pin functions are associated to the SRAM interface, the external SRAM
must be disabled when the bridge functionality is switched on.
External devices can be accessed by an address bus with up to 12 lines, an 8 bit data bus,
up to 8 chip select signals and two control lines supporting Motorola- or Siemens/Intel-Style
interfaces.
220 of 272
Pin
54 . . . 61
63 . . . 66
67 . . . 73
74
77 . . . 84
85
87
Table 11.2: HFC-E1 pins of the auxiliary bridge
1st function
SRA0 . . . SRA7
SRA8 . . . SRA11
SRA12 . . . SRA18
NC
SRD0 . . . SRD7
/SR_WR
/SR_OE
Auxiliary interface
Data Sheet
BRG_D0 . . . BRG_D7
2nd function
BRG_A0 . . . BRG_A7
BRG_A8 . . . BRG_A11
/BRG_CS0 . . . /BRG_CS6
/BRG_CS7
/BRG_WR
/BRG_RD
½
in the register V_BRG_EN.
March 2003 (rev. A)
Cologne
Chip