HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 45

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

2.1 Common features of all interface modes
2.1.1 EEPROM programming
The ISA PnP and PCMCIA interfaces require an external EEPROM. For the PCI bus and
the processor interface mode, this EEPROM is optional. The EEPROM programming spec-
ification is only available on special request from Cologne Chip to avoid destruction of
configuration information by not authorized programs or software viruses.
The EEPROM is used to store the configuration data for PCMCIA, PCI or ISA PnP. After a
reset (hardware reset or EEPROM load with V_RLD_EPR
the HFC-E1 copies a constant number of bytes from the EEPROM to the SRAM. The bytes
which are not used by the configuration data can be filled with vendor defined data. This data
(and the configuration data as well) can be read by RAM accesses to the HFC-E1. Tables 2.4
and 2.5 show how many bytes are copied in the different modes and which start address is
used for different SRAM sizes.
2.1.2 EEPROM circuitry
Figure 2.1 shows the connection of an EEPROM (e.g. 24C04 type) to the HFC-E1 pins
EE_SCL/EN and EE_SDA.
March 2003 (rev. A)
HFC-E1
Mode
ISA PnP mode
PCMCIA mode
PCI mode
parallel processor mode
Table 2.4: EEPROM load size
Number
Table 2.3: Overview of common bus interface pins
100
102
103
99
bytes copied
Number of
Universal external bus interface
Name
MODE0
MODE1
EE_SCL/EN
EE_SDA
512
512
512
128
Data Sheet
Description
Interface Mode pin 0
Interface Mode pin 1
EEPROM clock / EEPROM enable
EEPROM data I/O
Table 2.5: SRAM start address
SRAM size
128k x 8
512k x 8
32k x 8
½
of the register R_CIRM)
1
Start address
in SRAM
0x1A00
0x2A00
0x2A00
Cologne
Chip
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