HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 150

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
5.2 Clock synchronization
150 of 272
E1 interface
RX
TX
2.046 kHz
divider
÷ 256
8 kHz
PCM data
controller
JATT
receive
DPLL
2.048 kHz
controller
E1 data
frame
select
sync
sync
Figure 5.1: E1 clock synchronization
8 kHz
32.768 MHz
8 kHz
E1 interface
DPLL
PCM
Data Sheet
divider
select
1
0
or 8192 kHz
or 4096 kHz
MUX
select
16384 kHz
sync
MUX
select
input
sync
divider
÷ 2
MUX
divider
divider
÷ 2048
÷ 1024
÷ 512
÷ 2
output
sync
select
32.768 MHz
March 2003 (rev. A)
Cologne
PCM Master
Chip
PCM interface
8 kHz
SYNC_I
SYNC_O
C2O
C4IO
F0IO