HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 71

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

16 bit processors can either write data with byte or word access like shown in Figure 2.12.
FIFO write access have 8 bit or 16 bit width alternatively. The 16 bit processor must support
byte access because all other register write accesses must have a width of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 control the low byte and high byte of
the data bus D15 . . . D0 (see Table 2.19).
Data is written with
mode 3 (Intel, non-multiplexed). The HFC-E1 requires a data setup time
hold time
Address and /BE require a setup time
signals are valid. The hold time of these lines is
March 2003 (rev. A)
HFC-E1
/WR+/CS
/DS+/CS
/BE[3:2]
D[15:8]
A[7:0]
D[7:0]
Figure 2.12: Byte and word write access from 16 bit processors in mode 2 (Motorola) and mode 3 (Intel)
/BE1
/BE0
R/W
/RD
in mode2 only
(Motorola:)
in mode 3 only
(Intel):
Ø
Ï À
.
t
RWS
of (/DS
t
t
DWRS
DWRS
t
t
word write access
WR
WR
t
data
data
AS
byte enable
byte enable
address
Universal external bus interface
·
t
t
DWRH
DWRH
t
RWH
t
AH
/CS) in mode 2 (Motorola) respective (/WR
t
IDLE
Ø
Data Sheet
Ë
permanently high
permanently high
which starts when all address and byte enable
t
RWS
Ø
t
DWRS
t
t
low byte write access
WR
WR
À
t
data
AS
.
byte enable
byte enable
address
t
DWRH
t
RWH
t
AH
t
IDLE
t
RWS
high byte access
t
DWRS
t
t
WR
WR
Ø
t
data
AS
Ï Ë
byte enable
byte enable
address
t
Cologne
Chip
DWRH
·
and a data
t
RWH
t
AH
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/CS) in