HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 159

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_RX_FR1
E1 receive frame configuration, register 1
0
1
2
4..3
5
6
7
Bits
0
0
0
0
0
Value
Reset
(reserved)
Name
V_RX_MF
V_RX_MF_SYNC
V_RX_SL0_RAM
V_ERR_SIM
V_RES_NMF
(reserved)
(write only)
E1 interface
Data Sheet
Description
Multiframe mode
’0’ = normal doubleframe mode
’1’ = multiframe mode (CRC4)
Multiframe alignment error
’0’ = normal operation
’1’ = MFA error leads to loss of synchronization
Time slot 0 data destination
’0’ = time slot 0 data is written into HFC-channel 0
’1’ = time slot 0 data is written into alternating
RAM buffer
Must be ’00’.
Error simulation
This bit is for diagnostic purpose only.
’0’ = no action
’1’ = increment all error counters
Reset ‘no multiframe found’ (NMF) status
’0’ = no action
’1’ = reset no MFA found status which is set after
400 ms of MFA searching
This bit is automatically cleared.
Must be ’0’.
Cologne
Chip
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