HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 112

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
112 of 272
➋ FIFO-to-PCM
The following two list entries (indices 2 and 3) define the bidirectional FIFO-to-PCM
connections. Two E1 time slots are blocked. But E1 time slot resources are saved
because HFC-channels that are assigned to not used E-channels are selected.
A_CON_HDLC[0] : V_DATA_FLOW
A_CHANNEL[0] : V_CH_DIR0
A_FIFO_SEQ[0] : V_NEXT_FIFO_DIR
A_CON_HDLC[1] : V_DATA_FLOW
A_CHANNEL[1] : V_CH_DIR0
A_FIFO_SEQ[1] : V_NEXT_FIFO_DIR
A_CON_HDLC[2] : V_DATA_FLOW
A_CHANNEL[2]
R_SLOT
A_SL_CFG[21,RX] : V_CH_DIR1
A_FIFO_SEQ[2]
R_FSM_IDX
R_FSM_IDX
R_FSM_IDX
Table 3.4: List specification of the example in Figure 3.10
List index
0
1
2
3
4
5
6
7
: V_IDX
: V_IDX
: V_CH_NUM0
: V_NEXT_FIFO_NUM
: V_SEQ_END
: V_CH_NUM0
: V_NEXT_FIFO_NUM
: V_SEQ_END
: V_IDX
: V_CH_DIR0
: V_CH_NUM0
: V_SL_DIR
: V_SL_NUM
: V_CH_NUM1
: V_NEXT_FIFO_DIR
: V_NEXT_FIFO_NUM
: V_SEQ_END
FIFO[12,TX]
FIFO[12,RX]
FIFO[13,RX]
FIFO[13,TX]
FIFO[14,TX]
FIFO[14,RX]
FIFO[14,TX]
FIFO[14,RX]
Data Sheet
Data flow
Connection
E1 slot[12,TX]
E1 slot[12,TX]
PCM slot[21,RX]
PCM slot[21,TX]
E1 slot[17,TX]
E1 slot[17,RX]
E1 slot[20,TX]
E1 slot[20,RX]
0
’100’
0
12
1
12
0
1
’100’
1
12
1
13
0
2
’011’
1
1
21
1
0
13
0
15
15
(list index 0, FIFO[12,TX])
(FIFO
(transmit HFC-channel)
(next: receive FIFO)
(next: FIFO #12)
(list index 1, FIFO[12,RX])
(FIFO
(receive HFC-channel)
(next: receive FIFO)
(next: FIFO #13)
(HFC-channel #12)
(continue)
(HFC-channel #12)
(continue)
(list index 2, FIFO[13,RX])
(FIFO
(receive HFC-channel)
(receive slot)
(receive HFC-channel)
(next: transmit FIFO)
(HFC-channel #15)
(slot #21)
(HFC-channel #15)
(next: FIFO #13)
(continue)
E1)
E1)
March 2003 (rev. A)
PCM)
Cologne
Chip