HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 247

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_IRQ_FIFO_BL4
FIFO interrupt register for FIFO block 4
In HDLC mode the end of frame is signaled, while in transparent mode the fre-
quency of interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If
a bit is ’0’, no interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register
R_IRQ_OVIEW.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Value
Reset
Name
V_IRQ_FIFO16_TX
V_IRQ_FIFO16_RX
V_IRQ_FIFO17_TX
V_IRQ_FIFO17_RX
V_IRQ_FIFO18_TX
V_IRQ_FIFO18_RX
V_IRQ_FIFO19_TX
V_IRQ_FIFO19_RX
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Description
Interrupt occured in transmit FIFO 16
Interrupt occured in receive FIFO 16
Interrupt occured in transmit FIFO 17
Interrupt occured in receive FIFO 17
Interrupt occured in transmit FIFO 18
Interrupt occured in receive FIFO 18
Interrupt occured in transmit FIFO 19
Interrupt occured in receive FIFO 19
Cologne
Chip
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