HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 160

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
160 of 272
R_TX0
E1 transmitter configuration, register 0
1..0
2
3
4
5
6
7
Bits
G
Transmit data is only generated if V_OUT_EN bit of the register R_TX0
is set to ’1’.
0
0
0
0
0
0
0
Reset
Value
Important !
Name
V_TX_CODE
V_TX_FBAUD
V_TX_CMI_CODE
V_TX_INV_CMI_CODE
V_TX_INV_CLK
V_TX_INV_DATA
V_OUT_EN
(write only)
E1 interface
Data Sheet
Transmit code
Description
’00’ = NRZ (pin R_A is data output and pin R_B is
clock output in NRZ mode)
’10’ = AMI code
’01’ = HDB3 code
’11’ = reserved
Full / half bauded
’0’ = transmit pulse is half bit long
’1’ = transmit pulse is full bit long
Code mark inversion (CMI)
’0’ = CMI off
’1’ = CMI on (only R_A is used as data output)
Inverted CMI code
This bit is only valid if CMI is on.
’0’ = CMI code
’1’ = inverted CMI code
Polarity of clock
This bit is only valid if data clock output is enabled.
’0’ = non-inverted clock
’1’ = inverted clock
Polarity of output data
’0’ = non-inverted data
’1’ = inverted data
Buffer enable
’0’ = output buffers disabled (tristate)
’1’ = output buffers enabled
March 2003 (rev. A)
Cologne
Chip
0x28