HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 27

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

1.3.2 Pin list
March 2003 (rev. A)
HFC-E1
Pin
1
2
3
4
5
6
7
Interface
PCI
ISA PnP
PCMCIA
Processor
SPI
PCI
ISA PnP
PCMCIA
Processor
SPI
PCI
ISA PnP
PCMCIA
Processor
SPI
PCI
ISA PnP
PCMCIA
Processor
SPI
PCI
ISA PnP
PCMCIA
Processor
SPI
PCI
ISA PnP
PCMCIA
Processor
SPI
Name
FL0
FL0
FL0
FL0
/BE3
GND
AD27
SA11
A11
FL0
AD26
SA10
A10
FL0
AD25
SA9
A9
FL0
AD24
SA8
A8
FL0
GND
C/BE3#
FL1
FL1
FL1
IDSEL
GND
REG#
GND
I/O
IO
IO
IO
IO
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Universal bus interface
General description
Description
Address / Data bit 27
Fixed level (low), connect to
ground via ext. pull-down
Fixed level (low), connect to
Address / Data bit 26
Fixed level (low), connect to
ground via ext. pull-down
Fixed level (low), connect to
Address / Data bit 25
Fixed level (low), connect to
Fixed level (low), connect to
Address / Data bit 24
Fixed level (low), connect to
Fixed level (low), connect to
Ground
Fixed level (high), connect to
power supply via ext. pull-up
Fixed level (high), connect to
power supply via ext. pull-up
Byte Enable 3
Fixed level (high), connect to
power supply via ext. pull-up
Ground
Mem. Select
Ground
Ground
Address bit 11
Address bit 11
ground via ext. pull-down
Address bit 10
Address bit 10
ground via ext. pull-down
Address bit 9
Address bit 9
ground via ext. pull-down
ground via ext. pull-down
Address bit 8
Address bit 8
ground via ext. pull-down
ground via ext. pull-down
Bus command and Byte Enable 3
Initialisation Device Select
PCMCIA
Data Sheet
Register
and Attr.
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
(continued on next page)
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