HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 148

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
5.1 Interface functionality
The HFC-E1 is aquipped with a fully ETSI compliant (TBR4) E1 interface which handles
32 time slots of 8 bits each. The time slots are numbered 0 . . . 31. Slot 0 is used for
synchronization purposes and for the CRC4 prodcedure which checks for data integrity. All
other slots can be used for data transmission. In ISDN environments slot 16 is normally used
as D-channel.
The HFC-E1 provides the F/G state of the E1 interface in the register R_E1_WR_STA. It
is also implemented to force a specific state by overwriting the automatic E1 state machine.
Fundamental interface mode selections can be done by writing registers R_RX0 for receive
direction and R_TX0 for transmit direction. Fiber optical interface can be selcted by setting
V_RX_CODE and V_TX_CODE to NRZ. In this case R_A is data input and R_B is clock
input in receive direction; accordingly T_A is data output and T_B is clock output then.
For normal E1 operation with the interface circuit of Figure 5.3 and 5.4 the register R_RX0
should be set to 0x01.
148 of 272
Write only registers:
Address
0x2D
0x2E
0x20
0x22
0x23
0x24
0x25
0x26
0x28
0x29
0x30
0x31
0x34
0x35
0x38
0x39
0x46
Name
R_E1_WR_STA
R_LOS0
R_LOS1
R_RX0
R_RX_FR0
R_RX_FR1
R_TX0
R_TX1
R_TX_FR1
R_TX_FR2
R_RX_OFF
R_SYNC_OUT
R_TX_OFF
R_SYNC_CTRL
R_PWM0
R_PWM1
R_PWM_MD
Table 5.2: Overview of the HFC-E1 E1 interface registers
Page
155
155
156
157
158
159
160
161
163
164
165
166
167
168
197
197
198
E1 interface
Data Sheet
Read only registers:
Address
0x2C
0x3A
0x3B
0x20
0x24
0x25
0x26
0x27
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
Name
R_STATE
R_RX_STA0
R_RX_STA1
R_RX_STA2
R_RX_STA3
R_SLIP
R_FAS_ECL
R_FAS_ECH
R_VIO_ECL
R_VIO_ECH
R_CRC_ECL
R_CRC_ECH
R_E_ECL
R_E_ECH
R_SA6_SA13_ECL
R_SA6_SA13_ECH
R_SA6_SA23_ECL
R_SA6_SA23_ECH
March 2003 (rev. A)
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Cologne
Chip